On Mon, Oct 8, 2018 at 5:38 PM Arnd Bergmann <arnd@xxxxxxxx> wrote: > > On Sun, Oct 7, 2018 at 5:01 PM <sunil.kovvuri@xxxxxxxxx> wrote: > > > > > + /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence > > + * create a IOMMU mapping for the physcial address configured by > > + * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. > > + */ > > + cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); > > + max_msix = cfg & 0xFFFFF; > > + phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); > > + iova = dma_map_single(rvu->dev, (void *)phy_addr, > > + max_msix * PCI_MSIX_ENTRY_SIZE, > > + DMA_BIDIRECTIONAL); > > + if (dma_mapping_error(rvu->dev, iova)) > > + return -ENOMEM; > > + > > + rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); > > + rvu->msix_base_iova = iova; > > + > > I'm a bit puzzled by how this works. Does this rely on a specific iommu > driver implementation? Normally a physical address makes no sense to the > implementation backing dma_map_single() that tries to convert a > linear kernel virtual address into a physical address. > > Arnd I understand what you are pointing at, but we did test this. IOMMU on this silicon is standard ARM64 SMMUv3. All dma_map_single does is virt_to_page and iommu_dma_map_page converts it back i.e page_to_phys. So the IOMMU driver gets the same physical address passed above and creates a iova translation mapping. For reference below is the captured debug info for the same ===== [ 19.435968] rvu_setup_msix_resources: phy_addr 0x3200000 iova 0xfff80000 [ 19.436967] rvu_setup_msix_resources: virt_to_page(phy_addr) 0xffff7fe00000c800 page_to_phys(page) 0x3200000 offset_in_page(phy_addr) 0x00 ===== Thanks, Sunil.
