Quoting Doug Anderson (2018-03-29 13:55:55) > Hi, > > On Thu, Mar 29, 2018 at 4:04 AM, Manu Gautam <mgautam@xxxxxxxxxxxxxx> wrote: > > The USB and PCIE pipe clocks are sourced from external clocks > > inside the QMP USB/PCIE PHYs. Enabling or disabling of PIPE RCG > > clocks is dependent on PHY initialization sequence hence > > update halt_check to BRANCH_HALT_DELAY for these clocks so > > that clock status bit is not polled when enabling or disabling > > the clocks. It allows to simplify PHY client driver code which > > is both user and source of the pipe_clk and avoid error logging > > related status check on clk_disable/enable. > > > > Signed-off-by: Manu Gautam <mgautam@xxxxxxxxxxxxxx> > > --- > > drivers/clk/qcom/gcc-msm8996.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > As per my feedback on <https://patchwork.kernel.org/patch/10314937/>, > I'm not a fan of this. Hopefully we can adjust the PHY driver so it's > not needed. > Agreed. We should be able to enable the clks at the right time and halt bits should work. From what I can recall we had that working before on db820c, so has something changed? -- To unsubscribe from this list: send the line "unsubscribe linux-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
