Hi Abhishek,
On 3/16/2018 4:50 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> The driver/phy support for ipq8074 is available now.
>> So enabling the nodes in DT.
>>
>> Signed-off-by: Sricharan R <sricharan@xxxxxxxxxxxxxx>
>> ---
>> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +++++++++++++++++++++++++++++++++-
>> 1 file changed, 156 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index 806fc56..7562650 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -24,7 +24,7 @@
>> ranges = <0 0 0 0xffffffff>;
>> compatible = "simple-bus";
>>
>> - pinctrl@1000000 {
>> + tlmm: pinctrl@1000000 {
>> compatible = "qcom,ipq8074-pinctrl";
>> reg = <0x1000000 0x300000>;
>> interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -229,6 +229,161 @@
>> dma-names = "tx", "rx", "cmd";
>> status = "disabled";
>> };
>> +
>> + pcie_phy0: phy@86000 {
>> + compatible = "qcom,ipq8074-qmp-pcie-phy";
>> + reg = <0x86000 0x1000>;
>> + #phy-cells = <0>;
>> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>> + clock-names = "pipe_clk";
>> + clock-output-names = "pcie20_phy0_pipe_clk";
>> +
>> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
>> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
>> + reset-names = "phy",
>> + "common";
>> + status = "disabled";
>> + };
>> +
>> + pcie0: pci@20000000 {
>> + compatible = "qcom,pcie-ipq8074";
>> + reg = <0x20000000 0xf1d
>> + 0x20000F20 0xa8
>
> s/0x20000F20/0x20000f20
ok
>
>> + 0x80000 0x2000
>> + 0x20100000 0x1000>;
>> + reg-names = "dbi", "elbi", "parf", "config";
>> + device_type = "pci";
>> + linux,pci-domain = <0>;
>> + bus-range = <0x00 0xff>;
>> + num-lanes = <1>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> +
>> + phys = <&pcie_phy0>;
>> + phy-names = "pciephy";
>> +
>> + ranges = <0x81000000 0 0x20200000 0x20200000
>> + 0 0x00100000 /* downstream I/O */
>
> we can remove trailing zeros from address.
> s/0x00100000/0x100000
>
>> + 0x82000000 0 0x20300000 0x20300000
>> + 0 0x00d00000>; /* non-prefetchable memory */
>
> s/0x00d00000/0xd00000
>
> Same changes are for PCIE1 also.
ok
>
> With that.
>
> Reviewed-by: Abhishek Sahu <absahu@xxxxxxxxxxxxxx>
Thanks.
Regards,
Sricharan
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