On 2018-02-28 04:06, Andy Gross wrote:
On Sat, Feb 03, 2018 at 01:28:09PM +0530, Abhishek Sahu wrote:
A single BAM transfer can have multiple read and write messages.
The EOT and FLUSH tags should be scheduled at the end of BAM HW
descriptors. Since the READ and WRITE can be present in any order
so for some of the cases, these tags are not being written
correctly.
Signed-off-by: Abhishek Sahu <absahu@xxxxxxxxxxxxxx>
---
drivers/i2c/busses/i2c-qup.c | 54
++++++++++++++++++++------------------------
1 file changed, 24 insertions(+), 30 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qup.c
b/drivers/i2c/busses/i2c-qup.c
index bb83a2967..6357aff 100644
--- a/drivers/i2c/busses/i2c-qup.c
+++ b/drivers/i2c/busses/i2c-qup.c
@@ -560,7 +560,7 @@ static int qup_i2c_set_tags_smb(u16 addr, u8
*tags, struct qup_i2c_dev *qup,
}
static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
- struct i2c_msg *msg, int is_dma)
+ struct i2c_msg *msg)
{
u16 addr = i2c_8bit_addr_from_msg(msg);
int len = 0;
@@ -601,11 +601,6 @@ static int qup_i2c_set_tags(u8 *tags, struct
qup_i2c_dev *qup,
else
tags[len++] = data_len;
- if ((msg->flags & I2C_M_RD) && last && is_dma) {
- tags[len++] = QUP_BAM_INPUT_EOT;
- tags[len++] = QUP_BAM_FLUSH_STOP;
- }
-
So lets say you have multiple read and 1 write message. These changes
will send
a EOT/FLUSH for all reads. I think the intent here was that the last
read
message (not the last message) would have the EOT+FLUSH. Can there be
an issue
with sending EOT/FLUSH for all reads? And how does this mesh up with
the BAM
signaling?
Thanks Andy and Austin for reviewing these patches.
The role of FLUSH and EOT tag is to flush already scheduled descriptors
in HW. EOT is required only when descriptors are scheduled in RX FIFO.
If all the messages are WRITE, then only FLUSH tag will be used.
Let’s take following example
READ, READ, READ, READ
Currently EOT and FLUSH tags are being written after each READ. If we
get the NACK for first READ itself, then flush will be triggered. It
will look for first FLUSH tag in TX FIFO and will stop there so only
descriptors for first READ will be flushed. We need to clear all
scheduled descriptors to generate the completion.
Now this patch is scheduling FLUSH and EOT only once after all the
descriptors. So, flush will clear all the scheduled descriptors and
BAM will generate the completion interrupt. For multiple READ and
single WRITE also, this will work fine.
I tested with
- single xfer with multiple read messages
- single xfer with multiple write messages
- single xfer with multiple alternate read and write messages
for non-connected address in forceful DMA mode which will generate
the NACK for first byte itself.
Thanks,
Abhishek
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