On 11/25, Abhishek Sahu wrote: > The current ipq4019 clock driver registered the PLL clocks and > dividers as fixed clock. These fixed clock needs to be removed > from driver probe function and same need to be registered with > clock framework. These PLL clocks should be programmed only > once and the same are being programmed already by the boot > loader so the set rate operation is not required for these > clocks. Only the rate can be calculated by clock operations > in clock driver file so this patch adds the same. > > The PLL takes the reference clock from XO and generates the > intermediate VCO frequency. This VCO frequency will be divided > down by different PLL internal dividers. Some of the PLL > internal dividers are fixed while other are programmable. > > Signed-off-by: Abhishek Sahu <absahu@xxxxxxxxxxxxxx> > --- Applied to clk-ipq4019 and merged into clk-next. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
