On Wed, Feb 13, 2019 at 03:23:36PM -0800, Vineet Gupta wrote: > On 2/13/19 4:56 AM, Peter Zijlstra wrote: > > > > Personally I think u64 and company should already force natural > > alignment; but alas. > > But there is an ISA/ABI angle here too. e.g. On 32-bit ARC, LDD (load double) is > allowed to take a 32-bit aligned address to load a register pair. Thus all u64 > need not be 64-bit aligned (unless attribute aligned 8 etc) hence the relaxation > in ABI (alignment of long long is 4). You could certainly argue that we end up > undoing some of it anyways by defining things like ARCH_KMALLOC_MINALIGN to 8, but > still... So what happens if the data is then split across two cachelines; will a STD vs LDD still be single-copy-atomic? I don't _think_ we rely on that for > sizeof(unsigned long), with the obvious exception of atomic64_t, but yuck... So even though it is allowed by the chip; does it really make sense to use this? _______________________________________________ linux-snps-arc mailing list linux-snps-arc@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/linux-snps-arc
