On 11/30/18 5:57 AM, David Laight wrote: > There're even identical opcodes... > The barrier() (etc) in the asm output probably stopped the optimisation. > > It also seems to have used a different type of loop to the > other example, probably less efficient. > (Not that I'm an expert on ARC opcodes.) The difference is due to ISA and ensuing ARC gcc backends. ARCompact based cores don't support unaligned access and the loop there was ZOL (Zero delay loop). In ARCv2 based cores, the gcc backend has been tweaked to generate fewer ZOLs hence you see the more canonical tst and branch style loop. -Vineet _______________________________________________ linux-snps-arc mailing list linux-snps-arc@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/linux-snps-arc
