Hi, On Fri, 2017-04-21 at 18:13 +0300, Andy Shevchenko wrote: > On Fri, 2017-04-21 at 14:29 +0000, Eugeniy Paltsev wrote: > > On Tue, 2017-04-18 at 15:31 +0300, Andy Shevchenko wrote: > > > On Fri, 2017-04-07 at 17:04 +0300, Eugeniy Paltsev wrote: > > > > This patch adds support for the DW AXI DMAC controller. > > > > +#define AXI_DMA_BUSWIDTHS ??\ > > > > + (DMA_SLAVE_BUSWIDTH_1_BYTE | \ > > > > + DMA_SLAVE_BUSWIDTH_2_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_4_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_8_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_16_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_32_BYTES | \ > > > > + DMA_SLAVE_BUSWIDTH_64_BYTES) > > > > +/* TODO: check: do we need to use BIT() macro here? */ > > > > > > Still TODO? I remember I answered to this on the first round. > > > > Yes, I remember it. > > I left this TODO as a reminder because src_addr_widths and > > dst_addr_widths are > > not used anywhere and they are set differently in different drivers > > (with or without BIT macro). > > Strange. AFAIK they are representing bits (which is not the best > idea) in the resulting u64 field. So, anything bigger than 63 doesn't >?make sense. They are u32 fields!
