On Thu, Sep 29, 2016 at 12:48:03PM -0700, Vineet Gupta wrote: > > [1] There's an exception on 64-bit AMD CPUs because AMD blew it. > > Also, x86 NMI return is itself severely overcomplicated because we don't > > have good control over NMI nesting. > > For ARC (HS38 cores), there are 16 interrupt priorities (0-high, 15-lowest) and > each active interrupt has a bit in AUX_IRQ_ACTIVE. If a prio X is active, another > prio X can't be taken (you can only take higher prio). In that sense nmi (aka prio > 0) can't nest for us. Forget you ever read this; the reason for the nested NMIs on x86 is horrid, but here goes: The problem is that IRET, the only instruction capable of returning from _any_ trap/fault/interrupt context automagically unmasks NMIs. And we 'want' to take debug-traps and page-faults from NMI context. We use debug-traps to synchronize against self-modifying code without halting the entire machine. We 'need' page-faults for vmalloc backed memory, the vmalloc page tables are not globally propagated and we need (minor) faults to populate the page-tables on demand. And we need page-faults to do user-space access from NMI context (for the fixup_exception stuff). Returning from either trap or fault is done through IRET, which then unmasks NMIs, allowing another NMI to come in while we're still servicing one. We have quite the horror cabinet for dealing with this ;-)
