On Thu, Jun 25, 2020 at 10:59:31AM +0200, Borislav Petkov wrote:
> On Thu, Jun 18, 2020 at 01:08:25AM +0300, Jarkko Sakkinen wrote:
> > From: Sean Christopherson <sean.j.christopherson@xxxxxxxxx>
> >
> > Include SGX bit to the PF error codes and throw SIGSEGV with PF_SGX when
> > a #PF with SGX set happens.
> >
> > CPU throws a #PF with the SGX bit in the event of Enclave Page Cache Map
> ^
> set
>
> > (EPCM) conflict. The EPCM is a CPU-internal table, which describes the
> > properties for a enclave page. Enclaves are measured and signed software
> > entities, which SGX hosts. [1]
> >
> > Although the primary purpose of the EPCM conflict checks is to prevent
> > malicious accesses to an enclave, an illegit access can happen also for
> > legit reasons.
> >
> > All SGX reserved memory, including EPCM is encrypted with a transient
> > key that does not survive from the power transition. Throwing a SIGSEGV
> > allows user space software react when this happens (e.g. rec-create the
> ^
> to recreate
>
> > enclave, which was invalidated).
> >
> > [1] Intel SDM: 36.5.1 Enclave Page Cache Map (EPCM)
> >
> > Acked-by: Jethro Beekman <jethro@xxxxxxxxxxxx>
> > Signed-off-by: Sean Christopherson <sean.j.christopherson@xxxxxxxxx>
> > Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@xxxxxxxxxxxxxxx>
> > ---
> > arch/x86/include/asm/traps.h | 1 +
> > arch/x86/mm/fault.c | 13 +++++++++++++
> > 2 files changed, 14 insertions(+)
> >
> > diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h
> > index 714b1a30e7b0..ee3617b67bf4 100644
> > --- a/arch/x86/include/asm/traps.h
> > +++ b/arch/x86/include/asm/traps.h
> > @@ -58,5 +58,6 @@ enum x86_pf_error_code {
> > X86_PF_RSVD = 1 << 3,
> > X86_PF_INSTR = 1 << 4,
> > X86_PF_PK = 1 << 5,
> > + X86_PF_SGX = 1 << 15,
>
> Needs to be added to the doc above it.
I ended up with:
* bit 5 == 1: protection keys block access
* bit 6 == 1: inside SGX enclave
*/
/Jarkko
