On Wed, Apr 29, 2020 at 08:14:59AM -0700, Sean Christopherson wrote: > On Wed, Apr 29, 2020 at 08:23:29AM +0300, Jarkko Sakkinen wrote: > > On Sun, Apr 26, 2020 at 11:57:53AM -0500, Dr. Greg wrote: > > > On Wed, Apr 22, 2020 at 12:52:56AM +0300, Jarkko Sakkinen wrote: > > > > > > Good day, I hope the weekend is going well for everyone. > > > > > > > Intel(R) SGX is a set of CPU instructions that can be used by applications > > > > to set aside private regions of code and data. The code outside the enclave > > > > is disallowed to access the memory inside the enclave by the CPU access > > > > control. > > > > > > > > ... [ elided ] .. > > > > > > > > The current implementation requires that the firmware sets > > > > IA32_SGXLEPUBKEYHASH* MSRs as writable so that ultimately the kernel can > > > > decide what enclaves it wants run. The implementation does not create > > > > any bottlenecks to support read-only MSRs later on. > > > > > > It seems highly unlikely that a driver implementation with any type of > > > support for read-only launch control registers would ever get into the > > > kernel. All one needs to do is review the conversations that Matthew > > > Garrett's lockdown patches engender to get a sense of that, ie: > > > > > > https://lwn.net/Articles/818277/ > > > > We do not require read-only MSRs. > > Greg is pointing out the opposite, that supporting read-only MSRs is highly > unlikely to ever be supported in the mainline kernel. In a nutshell, what is wrong in the current code changes and what *exactly* should we change? This is way too high level at the moment at least for my limited brain capacity. /Jarkko
