On Mon, Jan 13, 2020 at 05:07:48PM +0100, Borislav Petkov wrote:
> On Mon, Jan 13, 2020 at 04:20:35PM +0100, Paolo Bonzini wrote:
> > Put them in too, it's even simpler.
>
> /me brews a fresh coffee and gets crackin'.
JFYI: there'll be a merge conflict, below is me merging into linux-next
from today.
Also, don't forget to fixup CPU_BASED_USE_TSC_OFFSETTING with "TT" since
you hav e
5e3d394fdd9e ("KVM: VMX: Fix the spelling of CPU_BASED_USE_TSC_OFFSETTING")
in your tree but this tree still has:
+ #define CPU_BASED_USE_TSC_OFFSETING VMCS_CONTROL_BIT(TSC_OFFSETTING)
Lemme know if there's something else I should do.
Thx.
---
diff --cc arch/x86/include/asm/vmx.h
index d716fe938fc0,9fbba31be825..000000000000
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@@ -19,27 -22,27 +22,73 @@@
/*
* Definitions of Primary Processor-Based VM-Execution Controls.
*/
++<<<<<<< HEAD
+#define CPU_BASED_INTR_WINDOW_EXITING 0x00000004
+#define CPU_BASED_USE_TSC_OFFSETTING 0x00000008
+#define CPU_BASED_HLT_EXITING 0x00000080
+#define CPU_BASED_INVLPG_EXITING 0x00000200
+#define CPU_BASED_MWAIT_EXITING 0x00000400
+#define CPU_BASED_RDPMC_EXITING 0x00000800
+#define CPU_BASED_RDTSC_EXITING 0x00001000
+#define CPU_BASED_CR3_LOAD_EXITING 0x00008000
+#define CPU_BASED_CR3_STORE_EXITING 0x00010000
+#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
+#define CPU_BASED_CR8_STORE_EXITING 0x00100000
+#define CPU_BASED_TPR_SHADOW 0x00200000
+#define CPU_BASED_NMI_WINDOW_EXITING 0x00400000
+#define CPU_BASED_MOV_DR_EXITING 0x00800000
+#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
+#define CPU_BASED_USE_IO_BITMAPS 0x02000000
+#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
+#define CPU_BASED_USE_MSR_BITMAPS 0x10000000
+#define CPU_BASED_MONITOR_EXITING 0x20000000
+#define CPU_BASED_PAUSE_EXITING 0x40000000
+#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
++||||||| merged common ancestors
++#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
++#define CPU_BASED_USE_TSC_OFFSETING 0x00000008
++#define CPU_BASED_HLT_EXITING 0x00000080
++#define CPU_BASED_INVLPG_EXITING 0x00000200
++#define CPU_BASED_MWAIT_EXITING 0x00000400
++#define CPU_BASED_RDPMC_EXITING 0x00000800
++#define CPU_BASED_RDTSC_EXITING 0x00001000
++#define CPU_BASED_CR3_LOAD_EXITING 0x00008000
++#define CPU_BASED_CR3_STORE_EXITING 0x00010000
++#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
++#define CPU_BASED_CR8_STORE_EXITING 0x00100000
++#define CPU_BASED_TPR_SHADOW 0x00200000
++#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
++#define CPU_BASED_MOV_DR_EXITING 0x00800000
++#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
++#define CPU_BASED_USE_IO_BITMAPS 0x02000000
++#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
++#define CPU_BASED_USE_MSR_BITMAPS 0x10000000
++#define CPU_BASED_MONITOR_EXITING 0x20000000
++#define CPU_BASED_PAUSE_EXITING 0x40000000
++#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
++=======
+ #define CPU_BASED_VIRTUAL_INTR_PENDING VMCS_CONTROL_BIT(VIRTUAL_INTR_PENDING)
+ #define CPU_BASED_USE_TSC_OFFSETING VMCS_CONTROL_BIT(TSC_OFFSETTING)
+ #define CPU_BASED_HLT_EXITING VMCS_CONTROL_BIT(HLT_EXITING)
+ #define CPU_BASED_INVLPG_EXITING VMCS_CONTROL_BIT(INVLPG_EXITING)
+ #define CPU_BASED_MWAIT_EXITING VMCS_CONTROL_BIT(MWAIT_EXITING)
+ #define CPU_BASED_RDPMC_EXITING VMCS_CONTROL_BIT(RDPMC_EXITING)
+ #define CPU_BASED_RDTSC_EXITING VMCS_CONTROL_BIT(RDTSC_EXITING)
+ #define CPU_BASED_CR3_LOAD_EXITING VMCS_CONTROL_BIT(CR3_LOAD_EXITING)
+ #define CPU_BASED_CR3_STORE_EXITING VMCS_CONTROL_BIT(CR3_STORE_EXITING)
+ #define CPU_BASED_CR8_LOAD_EXITING VMCS_CONTROL_BIT(CR8_LOAD_EXITING)
+ #define CPU_BASED_CR8_STORE_EXITING VMCS_CONTROL_BIT(CR8_STORE_EXITING)
+ #define CPU_BASED_TPR_SHADOW VMCS_CONTROL_BIT(VIRTUAL_TPR)
+ #define CPU_BASED_VIRTUAL_NMI_PENDING VMCS_CONTROL_BIT(VIRTUAL_NMI_PENDING)
+ #define CPU_BASED_MOV_DR_EXITING VMCS_CONTROL_BIT(MOV_DR_EXITING)
+ #define CPU_BASED_UNCOND_IO_EXITING VMCS_CONTROL_BIT(UNCOND_IO_EXITING)
+ #define CPU_BASED_USE_IO_BITMAPS VMCS_CONTROL_BIT(USE_IO_BITMAPS)
+ #define CPU_BASED_MONITOR_TRAP_FLAG VMCS_CONTROL_BIT(MONITOR_TRAP_FLAG)
+ #define CPU_BASED_USE_MSR_BITMAPS VMCS_CONTROL_BIT(USE_MSR_BITMAPS)
+ #define CPU_BASED_MONITOR_EXITING VMCS_CONTROL_BIT(MONITOR_EXITING)
+ #define CPU_BASED_PAUSE_EXITING VMCS_CONTROL_BIT(PAUSE_EXITING)
+ #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS VMCS_CONTROL_BIT(SEC_CONTROLS)
++>>>>>>> tip-x86-cpu
#define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
