Hello Paul, hello Alan, hello NXP,
I have an MPC8313 here and the problem that a change introduced in 2011
(i.e. 9deaa53ac7fa ("serial: add irq handler for Freescale 16550
errata.")) results in a bug. (Will send a fix for that in a separate
thread.)
The thing that bothers me is: The machine in question doesn't seem to
have the behaviour described in the chip erratum document[1]. I'm using
a MPC8313CVRAGDC, and even when I send a 10s long break, I only get a
single interrupt and LSR doesn't get the BI bit set after the first
event.
(The erratum applies to MPC8313E, the MPC8313 doesn't have a dedicated
errata document and reference manual. The latter states that it applies
to MPC8313, too, the errata document doesn't. As the difference betweeen
MPC8313 and MPC8313E is only an encryption engine I would expect that
the UART of the MPC8313 shows the same behaviour as the MPC8313E?!)
Do you have some information which CPUs are actually affected, or is
there a problem with my diagnosis that MPC8313CVRAGDC isn't affected?
@Paul: Do you still remember which machine you saw the problem on and
which version of the erratum you had at the time?
Best regards
Uwe
[1] General17 in https://www.nxp.com/docs/en/errata/MPC8313ECE.pdf
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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