On Thu, Jun 21, 2018 at 08:56:15AM +0200, Jan Kundrát wrote:
> On pátek 8. června 2018 14:27:00 CEST, Jan Kundrát wrote:
> > This chip has a diagnostics status bit informing about the state and
> > stability of the clock subsystem. According to the datasheet (STSint
> > register, bit 5, ClockReady), this bit works with the crystal
> > oscillator, but even without the PLL. Therefore:
> >
> > - ensure that the clock check is done even when PLL is not active
> > - warn when the chip thinks that the clock is not ready yet
> >
> > There are HW features which would let us wait asynchronously (there's a
> > maskable IRQ for that bit), but I think that even this simple check is a
> > net improvement. It would have saved me two days of debugging :).
> >
> > Signed-off-by: Jan Kundrát <jan.kundrat@xxxxxxxxx>
> > ---
> > drivers/tty/serial/max310x.c | 14 ++++++++++----
> > 1 file changed, 10 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c
> > index efe55a1a0615..3db48fcd6068 100644
> > --- a/drivers/tty/serial/max310x.c
> > +++ b/drivers/tty/serial/max310x.c
> > @@ -531,8 +531,8 @@ static int max310x_update_best_err(unsigned long f,
> > long *besterr)
> > return 1;
> > }
> > -static int max310x_set_ref_clk(struct max310x_port *s, unsigned long freq,
> > - bool xtal)
> > +static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
> > + unsigned long freq, bool xtal)
> > {
> > unsigned int div, clksrc, pllcfg = 0;
> > long besterr = -1;
> > @@ -588,8 +588,14 @@ static int max310x_set_ref_clk(struct max310x_port
> > *s, unsigned long freq,
> > regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
> > /* Wait for crystal */
> > - if (pllcfg && xtal)
> > + if (xtal) {
> > + unsigned int val;
> > msleep(10);
> > + regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val);
> > + if (!(val & MAX310X_STS_CLKREADY_BIT)) {
> > + dev_warn(dev, "clock is not stable yet\n");
> > + }
> > + }
> > return (int)bestfreq;
> > }
> > @@ -1260,7 +1266,7 @@ static int max310x_probe(struct device *dev,
> > struct max310x_devtype *devtype,
> > MAX310X_MODE1_AUTOSLEEP_BIT);
> > }
> > - uartclk = max310x_set_ref_clk(s, freq, xtal);
> > + uartclk = max310x_set_ref_clk(dev, s, freq, xtal);
> > dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
> > mutex_init(&s->mutex);
>
> Greg, can you review this patch, please?
$ mdfrm -c ~/mail/todo
1425 messages in /home/gregkh/mail/todo
It's in good company :)
Don't worry, it's not lost, I'm just at conferences for 2 weeks so patch
review is a bit delayed. Please relax, it will be handled...
greg k-h
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