On 12.06.2018 11:58, Uwe Kleine-König wrote:
> Initially when register shadowing was introduced (commit 3a0ab62f43de
> ("serial: imx: implement shadow registers for UCRx and UFCR")) the logic
> to handle UCR2_SRST was wrong but documented consistently. Later the
> handling was fixed, but the comment was not. This change makes up leeway
> for the latter.
>
> Fixes: 0aa821d846c0 ("serial: imx: fix cached UCR2 read on software reset")
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx>
> ---
> drivers/tty/serial/imx.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
> index c2fc6bef7a6f..758a67f3c8b3 100644
> --- a/drivers/tty/serial/imx.c
> +++ b/drivers/tty/serial/imx.c
> @@ -314,7 +314,8 @@ static u32 imx_uart_readl(struct imx_port *sport,
> u32 offset)
> /*
> * UCR2_SRST is the only bit in the cached registers that might
> * differ from the value that was last written. As it only
> - * clears after being set, reread conditionally.
I remember vaguely that I read that and concluded that clears can be
translated to the manuals deassert, which happens to be 1 in that
case...
> + * automatically becomes one after being cleared, reread
> + * conditionally.
Being more explicit and stating that the flag becomes 1 automatically
makes it clearer.
Reviewed-by: Stefan Agner <stefan@xxxxxxxx>
--
Stefan
> */
> if (!(sport->ucr2 & UCR2_SRST))
> sport->ucr2 = readl(sport->port.membase + offset);
--
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