On Thu, May 3, 2018 at 1:15 PM Karthikeyan Ramasubramanian <
kramasub@xxxxxxxxxxxxxx> wrote:
> While initiating TX, only the register reads need to be ordered. The
> register write order either is achieved due to data dependency or is
> not required.
> Use readl to achieve the read order and remove the unnecessary barrier.
> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@xxxxxxxxxxxxxx>
> ---
> drivers/tty/serial/qcom_geni_serial.c | 16 +++++++---------
> 1 file changed, 7 insertions(+), 9 deletions(-)
> diff --git a/drivers/tty/serial/qcom_geni_serial.c
b/drivers/tty/serial/qcom_geni_serial.c
> index 018ba21..b0b1aa3 100644
> --- a/drivers/tty/serial/qcom_geni_serial.c
> +++ b/drivers/tty/serial/qcom_geni_serial.c
> @@ -417,20 +417,18 @@ static void qcom_geni_serial_start_tx(struct
uart_port *uport)
> u32 status;
> if (port->xfer_mode == GENI_SE_FIFO) {
> - status = readl_relaxed(uport->membase + SE_GENI_STATUS);
> + /*
> + * readl ensures reading & writing of IRQ_EN register
> + * is not re-ordered before checking the status of the
> + * Serial Engine.
> + */
> + status = readl(uport->membase + SE_GENI_STATUS);
> if (status & M_GENI_CMD_ACTIVE)
> return;
> if (!qcom_geni_serial_tx_empty(uport))
> return;
> - /*
> - * Ensure writing to IRQ_EN & watermark registers are not
> - * re-ordered before checking the status of the Serial
> - * Engine and TX FIFO
> - */
> - mb();
> -
> irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
> irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
> @@ -894,7 +892,7 @@ static void qcom_geni_serial_set_termios(struct
uart_port *uport,
> static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
> {
> - return !readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
> + return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
> }
> #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
> --
> Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
Reviewed-by: Evan Green <evgreen@xxxxxxxxxxxx>
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