Hello Stefan, On Thu, Apr 19, 2018 at 11:37:23PM +0200, Stefan Agner wrote: > On 16.04.2018 17:35, Stefan Agner wrote: > > To reset the UART the SRST needs be cleared (low active). According > > to the documentation the bit will remain active for 4 module clocks > > until it is cleared (set to 1). > > > > Hence the real register need to be read in case the cached register > > indcates that the SRST bit is zero. > > > > This bug lead to wrong baudrate because the baud rate register got > > restored before reset completed in imx_flush_buffer. > > Given that you reviewed my other patch rather quickly, you might have > overlooked this one? no I didn't, still the ping was justified. I didn't look into it at once because I didn't feel like opening the refman. > Since it is a regression, this should go into v4.17 still... That's right, Reviewed-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx> I wonder what is different on your side that made it break. I didn't see any breakage and tested that on a handful of different machines. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
