Hi Uwe On 2017-12-18 at 13:44:43 +0100, Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx> wrote: > On Mon, Dec 18, 2017 at 10:52:52AM +0100, Tobias Klauser wrote: > > On 2017-12-18 at 10:41:48 +0100, Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx> wrote: > > > The UART can be operated without an irq. In this case a timer is setup > > > that regularily calls altera_uart_interrupt(). The receiving part > > > depends on pp->imr having the bit ALTERA_UART_STATUS_RRDY_MSK set, > > > otherwise altera_uart_rx_chars() is never called. So ensure that the bit > > > gets set (disguised as ALTERA_UART_CONTROL_RRDY_MSK) by not returning > > > early from altera_uart_startup() if port->irq is 0. > > > > While the above is true, I don't think your patch is entriely correct. > > Now we would write ALTERA_UART_STATUS_RRDY_MSK to the control register > > which would enable read-ready interrupts even in IRQ-less mode (see > > Table 69 in [1]). > > > > [1] https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf > > Where does it hurt that an irq is enabled in irq-less mode? Whatever is connected to the Avalon-MM which doesn't expect interrupts from the UART. AFAIK there is not way to configure the UART core without interrupts, so it will always output an IRQ signal interrupt if the RRDY bit is set in the control register, cf. "8.5.4 Interrupt Behavior" in [1]. I guess the above is really a corner case and most users won't care but I'd still prefer to avoid it if possible, unless there is a convincing reason not to. -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
