On Wed, Nov 29, 2017 at 9:39 AM, Greentime Hu <green.hu@xxxxxxxxx> wrote:
> 2017-11-27 22:21 GMT+08:00 Arnd Bergmann <arnd@xxxxxxxx>:
>> On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <green.hu@xxxxxxxxx> wrote:
>>> diff --git a/arch/nds32/Kconfig.cpu b/arch/nds32/Kconfig.cpu
>>> +config CPU_CACHE_NONALIASING
>>> + bool "Non-aliasing cache"
>>> + help
>>> + If this CPU is using VIPT data cache and its cache way size is larger
>>> + than page size, say N. If it is using PIPT data cache, say Y.
>>> +
>>> + If unsure, say Y.
>>
>> Can you determine this from the CPU type?
>
> There is no cpu register to determine it. It also depeneds on page
> size and way size however page size is configurable by software.
> These codes are determined at compile time will be benefit to code
> size and performance.
> IMHO, I think it would be better to be determined here.
I meant determining it at compile time from other Kconfig symbols,
if that's possible. Do the CPU cores each have a fixed way-size?
If they do, it could be done like
menu "CPU selection"
config CPU_N15
bool "AndesCore N15"
select CPU_CACHE_NONALIASING
config CPU_N13
bool "AndesCore N15"
select CPU_CACHE_NONALIASING if PAGE_SIZE_16K
...
endmenu
and then you can use the same CPU_... symbols to make other decisions
as well, e.g. CPU specific compiler optimizations.
Arnd
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