On Tue, 2017-08-22 at 16:20 +0300, Andy Shevchenko wrote:
> It used to be a gap in port definitions after PORT_MAX_8250. Since the
> new drivers are coming the gap become shorter and shorter until the
> commit a2d6a987bfe4 ("serial: 8250: Add new port type for TI
> DA8xx/66AK2x")
> completely removed it.
>
> So, while type here is just a formality, make things a little bit more
> explicit for this driver and move port types to UAPI header. Note,
> it uses two types for now.
>
Found more issues with the list.
Will resend this as patch 1 in v2 of patch series.
Also it seems the author is not working for Freescale anymore. Will try
another person for Cc list.
> Fixes: fddceb8b5399 ("tty: 8250: Add 64byte UART support for FSL
> platforms")
> Cc: Vijay Rai <vijay.rai@xxxxxxxxxxxxx>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
> ---
> drivers/tty/serial/pch_uart.c | 35 +++++++++++++++--------------
> ------
> include/uapi/linux/serial_core.h | 5 ++++-
> 2 files changed, 19 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/tty/serial/pch_uart.c
> b/drivers/tty/serial/pch_uart.c
> index c3390dd5c1ca..f764f906400c 100644
> --- a/drivers/tty/serial/pch_uart.c
> +++ b/drivers/tty/serial/pch_uart.c
> @@ -46,11 +46,6 @@ enum {
> PCH_UART_HANDLED_LS_INT_SHIFT,
> };
>
> -enum {
> - PCH_UART_8LINE,
> - PCH_UART_2LINE,
> -};
> -
> #define PCH_UART_DRIVER_DEVICE "ttyPCH"
>
> /* Set the max number of UART port
> @@ -267,7 +262,7 @@ struct eg20t_port {
>
> /**
> * struct pch_uart_driver_data - private data structure for UART-DMA
> - * @port_type: The number of DMA channel
> + * @port_type: The type of UART port
> * @line_no: UART port line number (0, 1,
> 2...)
> */
> struct pch_uart_driver_data {
> @@ -290,17 +285,17 @@ enum pch_uart_num_t {
> };
>
> static struct pch_uart_driver_data drv_dat[] = {
> - [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
> - [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
> - [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
> - [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
> - [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
> - [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
> - [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
> - [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
> - [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
> - [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
> - [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
> + [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
> + [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
> + [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
> + [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
> + [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
> + [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
> + [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
> + [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
> + [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
> + [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
> + [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
> };
>
> #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
> @@ -1776,10 +1771,10 @@ static struct eg20t_port
> *pch_uart_init_port(struct pci_dev *pdev,
> goto init_port_free_txbuf;
>
> switch (port_type) {
> - case PORT_UNKNOWN:
> + case PORT_PCH_8LINE:
> fifosize = 256; /* EG20T/ML7213: UART0 */
> break;
> - case PORT_8250:
> + case PORT_PCH_2LINE:
> fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
> break;
> default:
> @@ -1803,7 +1798,7 @@ static struct eg20t_port
> *pch_uart_init_port(struct pci_dev *pdev,
>
> priv->fifo_size = fifosize;
> priv->uartclk = pch_uart_get_uartclk();
> - priv->port_type = PORT_MAX_8250 + port_type + 1;
> + priv->port_type = port_type;
> priv->port.dev = &pdev->dev;
> priv->port.iobase = iobase;
> priv->port.membase = NULL;
> diff --git a/include/uapi/linux/serial_core.h
> b/include/uapi/linux/serial_core.h
> index 38bea3217ead..502aa23c7e15 100644
> --- a/include/uapi/linux/serial_core.h
> +++ b/include/uapi/linux/serial_core.h
> @@ -57,7 +57,6 @@
> #define PORT_RT2880 29 /* Ralink RT2880 internal UART
> */
> #define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64
> FIFOs */
> #define PORT_DA830 31 /* TI DA8xx/66AK2x */
> -#define PORT_MAX_8250 31 /* max port ID */
>
> /*
> * ARM specific type numbers. These are not currently guaranteed
> @@ -77,6 +76,10 @@
> #define PORT_SUNZILOG 38
> #define PORT_SUNSAB 39
>
> +/* Intel EG20 */
> +#define PORT_PCH_8LINE 44
> +#define PORT_PCH_2LINE 45
> +
> /* DEC */
> #define PORT_DZ 46
> #define PORT_ZS 47
--
Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Intel Finland Oy
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