On Mon, Jan 30, 2017 at 09:12:12AM -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@xxxxxxx>
>
> When userspace passes the SER_RS485_RTS_ON_SEND flag it means that the
> CTS_B pin should go to logic level high before the transmission begins.
>
> CTS_B goes to logic level high when both CTSC and CTS bits are cleared.
>
> When userspace passes the SER_RS485_RTS_AFTER_SEND flag it means that the
> CTS_B pin should go to logic level low after the transmission finishes.
>
> CTS_B goes to logic level low when CTSC bit is cleared and CTS bit is set.
>
> So fix the CTS_B polarity logic.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@xxxxxxx>
> ---
> I do not have access to a board that uses CTS_B pin connected to a
> RS485 transceiver.
>
> I have tested with a scope that the polarity of CTS_B is correct when
> this patch is applied.
>
> drivers/tty/serial/imx.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
> index 29dd57c..e3e152c 100644
> --- a/drivers/tty/serial/imx.c
> +++ b/drivers/tty/serial/imx.c
> @@ -336,15 +336,15 @@ static void imx_port_ucrs_restore(struct uart_port *port,
>
> static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
> {
> - *ucr2 &= ~UCR2_CTSC;
> - *ucr2 |= UCR2_CTS;
> + *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
>
> mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
> }
>
> static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
> {
> - *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
> + *ucr2 &= ~UCR2_CTSC;
> + *ucr2 |= UCR2_CTS;
>
> mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
> }
> --
> 2.7.4
>
Tested-by: Clemens Gruber <clemens.gruber@xxxxxxxxxxxx>
Regards,
Clemens
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