[PATCH] HW Flocontrol fix for SC16IS7XX UART driver

[Kim Bøndergaard Poulsen <Kim.BondergaardPoulsen@xxxxxxxxx>]

Following patch fixes HW flowcontrol issues with UARTs based in SC16IS7XX

I've only tested the patch with an SC16IS750. 

commit 9390e7e2952cac5e0119a656a0d8a4e8efe33d07
Author: Kim Bøndergaard <kibo@xxxxxxxxx>
Date:   Tue Mar 8 12:31:21 2016 +0100

    sc16is7xx: Fix HW flow control

    Following problems fixed:

    In sc16is7xx_set_baud() what ever was already set in
    EFR.CTS and EFT.RTS was cleared.

    In sc16is7xx_set_termios() enhanced functions where disabled

    In sc16is6xx_set_termios() upper layer is informed that this driver
    support automatic HW flowcontrol. Without this knowledge the two layers
    eventually ended up in different states, causing communication to stop

diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c
index 13f8d5f..5a51024 100644
--- a/drivers/tty/serial/sc16is7xx.c
+++ b/drivers/tty/serial/sc16is7xx.c
@@ -511,8 +511,9 @@ static int sc16is7xx_set_baud(struct uart_port *port, int baud)

        /* Enable enhanced features */
        regcache_cache_bypass(s->regmap, true);
-       sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
-                            SC16IS7XX_EFR_ENABLE_BIT);
+       sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
+                       SC16IS7XX_EFR_ENABLE_BIT,
+                       SC16IS7XX_EFR_ENABLE_BIT);
        regcache_cache_bypass(s->regmap, false);

        /* Put LCR back to the normal mode */
@@ -901,14 +902,19 @@ static void sc16is7xx_set_termios(struct uart_port *port,
        regcache_cache_bypass(s->regmap, true);
        sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
        sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
-       if (termios->c_cflag & CRTSCTS)
+       if (termios->c_cflag & CRTSCTS) {
                flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
                        SC16IS7XX_EFR_AUTORTS_BIT;
+               port->status |= UPSTAT_AUTOCTS;
+       }
        if (termios->c_iflag & IXON)
                flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
        if (termios->c_iflag & IXOFF)
                flow |= SC16IS7XX_EFR_SWFLOW1_BIT;

+       /* Always set enable enhanced */
+       flow |= SC16IS7XX_EFR_ENABLE_BIT;
+
        sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
        regcache_cache_bypass(s->regmap, false);
--
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