Hi!
Recently I've met an issue which, I guess, requires architectural
changes in virt-chan API.
The setup. UART (16750) with DMA engine (drivers/dma/hsu/) on Intel
Edison board (Tangier SoC). Both are different PCI devices.
HSU DMA Documentation states in particular "
If the UART receives data that does not reach the size of the minimum
bus transfer size, than this data remains in the buffer and is never
delivered to the memory by the DMA.
In order to resolve such potential problem, the UART generates a
timeout interrupt to the DMA. This interrupt is not dependent on the
timeout enable bit in the UART but is always enabled.
Once the DMA receives such an interrupts, it will start emptying the
FIFO and assert its own timeout interrupt to the CPU."
UART documentation states
"Receiver Timeout Interrupt
This interrupt only occurs in FIFO mode."
Our current DMA <-> UART work flow relies on UART Timeout Interrupt,
which is not happen in this case.
What DMA Engine API provides us? The callback function and possibility
to call a _tx_status() from it. During completion tasklet the flow
looks like this:
1. Split completed descriptor to local list.
2. Get callback functions for first descriptor in the list.
3. Free the descriptor.
4. Call callback. <<< descriptor related information is gone already!
That means that current work flow for DMA <-> UART is not sufficient
since it doesn't allow caller to get the actual amount of data
transfered.
So, what I see is should be done here in order to fulfill UART needs.
1. We have to handle properly timeout interrupt in the DMA driver and
call completion for the descriptor.
2. Somehow be sure that the descriptor under question is accessible
during callback when _tx_status() is called.
3. Fill residue even for completed descriptor (when cookie is in
DMA_COMPLETE status).
For now on I have no (good) ideas about implementation, nor anything
else in mind how to achieve it.
I would like to hear experienced guys what maybe I missed here or
didn't look at. Any proposals how to get this fixed in generic manner.
--
Andy Shevchenko <andriy.shevchenko@xxxxxxxxx>
Intel Finland Oy
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