Re: [PATCH 5/5] serial: 8250_mid: add support for DMA engine handling from UART MMIO

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> > +#define DNV_DMA_REGS	0x80
> > +#define DNV_DMA_OFFSET	0x40
> > +
> > +static int dnv_setup(struct mid8250 *mid, struct uart_port *p)
> > +{
> > +	struct hsu_dma_chip *chip = &mid->dma_chip;
> > +	struct pci_dev *pdev = to_pci_dev(p->dev);
> > +	int ret;
> > +
> > +	chip->dev = &pdev->dev;
> > +	chip->irq = pdev->irq;
> > +	chip->regs = p->membase + DNV_DMA_REGS;
> > +	chip->length = pci_resource_len(pdev, 0) - DNV_DMA_REGS;
> > +	chip->offset = DNV_DMA_OFFSET;
> 
> This a bit buggy, since that offset stuff is coming for HSU PCI case
> where we have
> 1) 0x100 bytes for global DMA registers (like interrupt)
> 2) 0x40 * nr_channels
> 
> So, in your case chip->offset should be 0, but _DMA_REGS should be
> renamed to something like DMA_REGS_START since it's an offset to UART
> register space.

Good catch! I'll prepare v2 of this series today and fix that.


Thanks Andy,

-- 
heikki
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