On Fri, Aug 07, 2015 at 10:41:57AM +0200, Sebastian Andrzej Siewior wrote: > This DMA driver is used by 8250-omap on DRA7-evm. There is one > requirement that is to pause a transfer. This is currently used on the RX > side. It is possible that the UART HW aborted the RX (UART's RX-timeout) > but the DMA controller starts the transfer shortly after. > Before we can manually purge the FIFO we need to pause the transfer, > check how many bytes it already received and terminate the transfer > without it making any progress. > > >From testing on the TX side it seems that it is possible that we invoke > pause once the transfer has completed which is indicated by the missing > CCR_ENABLE bit but before the interrupt has been noticed. In that case the > interrupt will come even after disabling it. How do you cope with the OMAP DMA hardware clearing its FIFO when you pause it? The problem is that on mem-to-device transfers, the DMA hardware can prefetch some data from memory into its FIFO before the device wants the data. If you then disable the channel, the hardware clears the FIFO. It is unspecified whether the hardware updates the source address in this case, or by how much. So it's pretty hard to undo the prefetching in software. The net result is: data loss. This is why I explicitly did not implement pause/resume for non-cyclic channels. -- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
