According to the datasheet, SCIFs on SoCs using SCIx_SH7705_SCIF_REGTYPE
(sh7705, sh7720, and sh7721) have 64-stage FIFO registers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
Untested due to lack of hardware.
---
drivers/tty/serial/sh-sci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index f1591b243bccb2bf..583aa563d4038f8b 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2272,12 +2272,13 @@ static int sci_init_single(struct platform_device *dev,
sampling_rate = 16;
break;
case PORT_SCIF:
- port->fifosize = 16;
if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
+ port->fifosize = 64;
sci_port->overrun_reg = SCxSR;
sci_port->overrun_mask = SCIFA_ORER;
sampling_rate = 16;
} else {
+ port->fifosize = 16;
sci_port->overrun_reg = SCLSR;
sci_port->overrun_mask = SCLSR_ORER;
sampling_rate = 32;
--
1.9.1
--
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