On Mon, Mar 30, 2015 at 04:26:52PM +0200, Jakub Kicinski wrote: > On Mon, 30 Mar 2015 13:28:40 +0100, Dave Martin wrote: [...] > > TXIS reflects the live status of the FIFO, except that it is > > "spuriously" deasserted betweem reset/clear of the interrupt and the > > first TX IRQ, even though the FIFO may be empty. > > I missed that IRQ is cleared by writing data. No worries, it took me a fair while to be sure of that myself. The TRM is not very clear on it. Thanks for the careful review. Cheers ---Dave -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
