Hi all,
I found that the base clock of PCIE958 (in 950 mode) is 62.5MHz.
So, i think it is necessary to change the 8250_pci.c to use 62.6MHz instead 64MHz
my patch attached, could you please send it to the kernel community for a review and
finally commit it?
>From 43ea641f6b75697373e6aae1287d1d6a2dce3730 Mon Sep 17 00:00:00 2001
From: goodmen <goodmenlinux@xxxxxxxxx>
Date: Sun, 22 Mar 2015 15:15:45 +0800
Subject: [PATCH] change OXPCIe958 8xUART base_baud to 62.5/16MHz
Signed-off-by: goodmen <goodmenlinux@xxxxxxxxx>
---
drivers/tty/serial/8250/8250_pci.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index 892eb32..e7ed89e 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -3418,6 +3418,13 @@ static struct pciserial_board pci_boards[] = {
.uart_offset = 0x200,
.first_offset = 0x1000,
},
+ [pbn_oxsemi_4_3906250] = {
+ .flags = FL_BASE0,
+ .num_ports = 4,
+ .base_baud = 3905250,
+ .uart_offset = 0x200,
+ .first_offset = 0x1000,
+ },
[pbn_oxsemi_4_4000000] = {
.flags = FL_BASE0,
.num_ports = 4,
@@ -4440,7 +4447,7 @@ static struct pci_device_id serial_pci_tbl[] = {
pbn_oxsemi_4_4000000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_8_4000000 },
+ pbn_oxsemi_8_3905250 },
{ PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_8_4000000 },
--
2.3.3
