One Thousand Gnomes <gnomes@xxxxxxxxxxxxxxxxxxx> wrote:
>> + baud = uart_get_baud_rate(port, termios, old,
>> + port->uartclk / 16 / 0xffff,
>> + port->uartclk / 16);
>> + switch (baud) {
>> + case 2400:
>> + len |= 1;
>> + break;
>> + case 4800:
>> + len |= 2;
>> + break;
>> + case 19200:
>> + len |= 4;
>> + break;
>> + case 38400:
>> + len |= 5;
>> + break;
>> + case 57600:
>> + len |= 6;
>> + break;
>> + case 115200:
>> + len |= 7;
>> + break;
>> + case 9600:
>> + default:
>> + len |= 3;
>> + break;
>> + };
>
>Some explanation of this would be useful - eg why is it set to 7 for
>115200 baud and 3 for 115201 baud ?
I am not related to the device vendor in any way, so please take my answers for what they are worth.
It seems that there is not enough pins to properly connect the chips to the memory bus and just you the standard 8250 UART driver. Instead, clock divisor is set using this register.
So, if you know you're asking for (115200) you get it. If you don't or guess (115201), you get the default 9600.
This is a policy, it may not be the right way to write a driver, but it is cheap and it works.
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