On Tue, Feb 28, 2012 at 10:35:30AM +0900, Chanho Min wrote: > On Mon, Feb 27, 2012 at 8:02 PM, Russell King - ARM Linux > <linux@xxxxxxxxxxxxxxxx> wrote: > > On Mon, Feb 27, 2012 at 10:48:58AM +0000, Russell King - ARM Linux wrote: > >> I'd much prefer to only clear those interrupts which actually need to be > >> cleared at this point. So, I'd suggest this approach instead: > > > > Thinking about this a little more, we definitely want to mask and clear > > interrupts at probe time as well: > > > I'm not satisfied with this completely. RIS has some pending > interrupts even if interrupts are masked/disabled in IMSC. If your > patch is applied, interrupt can be pended as bellows and RXFE of the > flag register is set as well. RXFE _will_ be set. Think about it - RXFE means Receive Fifo Empty. If the receive fifo is empty, it _will_ be set. And RIS is the _Raw_ interrupt status. That's the status _before_ the mask is acted upon. > writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS | > UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR); > ... > Interrupt is occured and pended in RIS But it won't be delivered because the mask register is zero. > .. > writew(uap->im, uap->port.membase + UART011_IMSC); > > Root cause is that Rx interrupt set but Rx fifo is empty. If we just > remove the sentence for clearing LCRH, nothing happens and interrupt > handler don't this misbehave. No. -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
