On Mon, Feb 27, 2012 at 10:30 AM, Chanho Min <chanho0207@xxxxxxxxx> wrote: > This is another workaroud of 'https://lkml.org/lkml/2012/1/17/104' > with additional analysis.Bootloader can transfer control to kernel and > there are some pending interrupts. In this case, RXFE of the flag > register is set by clearing FEN(LCRH) even if rx data remains in the > fifo. It seems that the fifo's status is initiailized. Interrupt > handler can not get any data from data register because of the below > break condtion. > > pl011_fifo_to_tty > while (max_count--) { > if (status & UART01x_FR_RXFE) > break; > > Then, Rx interrupt is never cleared. cpu is looping in ISR. System is > hang. If we don't guarantee that no interrupt is pended until fifo is > disabled by calling 'writew(0, uap->port.membase + uap->lcrh_rx)', > this misbehave of the interrupt handelr can be occurred. So, All > pending interrupts should be cleared just after fifo is disabled under > the protection from interrupt. Also,'clear error interrupts' routine > can be removed becuase all interrupts are cleared before. > > Signed-off-by: Chanho Min <chanho.min@xxxxxxx> Looks correct to me. Acked-by: Linus Walleij <linus.walleij@xxxxxxxxxx> Thanks, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
