On 02/21/2012 03:43 PM, Tomoya MORINAGA wrote: > 2012年2月22日1:07 Darren Hart <dvhart@xxxxxxxxxxxxxxx>: >> When does the phub driver update the clock registers? > > I've already posted pch_phub patch for 192MHz setting. > You can see the patch form below. Yes, I applied the patch. The problem seems to be this: DVHART: parse_options (8250_early.c) DVHART: pch_console_setup DVHART: pch_console_setup DVHART: pch_phub_probe: set CLKCFG UART to 192MHz As you can see, the pch_phub_probe happens much too late. I can get it to work with a boot command line like this: earlycon=uart8250,io,0x2050,115200n8 console=ttyPCH1,115200n8 And hacking all the BASE_BAUD references to be 48000000 (my current hardware sets the clock to 48MHz in firmware). This gets things working until pch_phub gets around to setting the CLKCFG register for the UART clock. I'd prefer to not have to use the earlycon parameter/code, but we need a way for the pch_uart to understand the difference between early boot and post-phub setup. Can we read the CLKCFG register in pch_console_setup to dynamically configure the port->uartclk? (not sure that's even the right place to do it). -- Darren >>> Signed-off-by: Tomoya MORINAGA <tomoya.rohm@xxxxxxxxx> >>> --- >>> Related patch is >>> http://marc.info/?l=linux-kernel&m=132979974907774&w=2 > > --- > ROHM Co., Ltd. > tomoya -- Darren Hart Intel Open Source Technology Center Yocto Project - Linux Kernel -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
