On 08/01/2016 14:52, Mark Rutland wrote:
On Fri, Jan 08, 2016 at 10:15:20PM +0800, John Garry wrote:
Add the dt bindings for HiSi SAS controller v2 HW.
The main difference in the controllers from dt perspective
is interrupts.
Signed-off-by: John Garry <john.garry@xxxxxxxxxx>
---
.../devicetree/bindings/scsi/hisilicon-sas.txt | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
index 0a7a325..2695023 100644
--- a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
+++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
@@ -5,6 +5,7 @@ The HiSilicon SAS controller supports SAS/SATA.
Main node required properties:
- compatible : value should be as follows:
(a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
+ (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
- sas-addr : array of 8 bytes for host SAS address
- reg : Address and length of the SAS register
- hisilicon,sas-syscon: phandle of syscon used for sas control
@@ -13,11 +14,11 @@ Main node required properties:
- ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
- queue-count : number of delivery and completion queues in the controller
- phy-count : number of phys accessible by the controller
- - interrupts : Interrupts for phys, completion queues, and fatal
+ - interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal
sources; the interrupts are ordered in 3 groups, as follows:
- - Phy interrupts
- - Completion queue interrupts
- - Fatal interrupts
+ - Phy interrupts
+ - Completion queue interrupts
+ - Fatal interrupts
Phy interrupts : Each phy has 3 interrupt sources:
- broadcast
- phyup
@@ -25,11 +26,28 @@ Main node required properties:
The phy interrupts are ordered into groups of 3 per phy
(broadcast, phyup, and abnormal) in increasing order.
Completion queue interrupts : each completion queue has 1
- interrupt source.
- The interrupts are ordered in increasing order.
+ interrupt source. The interrupts are ordered in
+ increasing order.
Fatal interrupts : the fatal interrupts are ordered as follows:
- ECC
- AXI bus
+ For v2 hw: Interrupts for phys, Sata, and completion queues;
+ the interrupts are ordered in 3 groups, as follows:
+ - Phy interrupts
+ - Sata interrupts
+ - Completion queue interrupts
+ Phy interrupts : Each controller has 2 phy interrupts:
+ - phy up/down
+ - channel interrupt
+ Sata interrupts : Each phy on the controller has 1 Sata
+ interrupt. The interrupts are ordered in increasing
+ order.
+ Completion queue interrupts : each completion queue has 1
+ interrupt source. The interrupts are ordered in
+ increasing order.
There are no fatal interrupts in V2?
For v2 hardware, broadcast and fatal interrupts are mutliplexed into the
general purpose channel interrupt line.
+Optional main node properties:
+ - am-max-trans : limit controller for am max transmissions
Is this a boolean? Number?
This is a boolean. It is for dealing with a quirk in the chipset: an
instance of the controller in the hip06 chipset requires registers set
with a different init value.
Thanks,
Mark.
thanks,
john
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