> +/** > + * SCIC_SWAP_DWORD() - > + * > + * Normal byte swap macro > + */ > +#define SCIC_SWAP_DWORD(x) \ > + (\ > + (((x) >> 24) & 0x000000FF) \ > + | (((x) >> 8) & 0x0000FF00) \ > + | (((x) << 8) & 0x00FF0000) \ > + | (((x) << 24) & 0xFF000000) \ > + ) Duplicates the kernel byte sewap macros. Even worse it's doing an unconditional swap instead of a conditional one if the platform is big endian. While we're at it this driver seems to lack any kind of endiness awareness, but that's probably to be expected coming from intel. Isn't the new chipset generation supposed to support ia64 as well, which is capable of running in big endian mode? -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
