On Thu, 5 Jun 2008 22:48:13 -0700 "Grant Grundler" <grundler@xxxxxxxxxx> wrote: > On Thu, Jun 5, 2008 at 9:44 PM, FUJITA Tomonori > <fujita.tomonori@xxxxxxxxxxxxx> wrote: > ... > > The current Intel IOMMU scheme is a bit unbalanced. It invalidates the > > translation table every time dma_unmap_* is called, but it does the > > batching of the TLB flushes. But it's what the most of Linux's IOMMU > > code does. > > > > I think that only PARISC (and IA64, of course) IOMMUs do the batching > > of invalidating the translation table entries. > > 1/2 correct. PARISC and IA64 could be the same in this regard but are not. > See where sba_mark_invalid() is called in the respective sba_iommu.c. > PARISC invalidates the IO Pdir entry immediately but batches the > IO TLB shootdown and resource "free". IA64 could (and probably should) > do the same. Added Alex Williamson and Bjorn Helgaas to CC list. > Not an urgent issue though unless they are doing perf measurements > with SSDs or other block device with equivalent IOPS. Oops, thanks. Seems that IA64 does the batching of sba_mark_invalid, sba_free_range, and flushing TLB. IA64 and PARISC look different in this regard. -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
