Re: Process Scheduling Issue using sg/libata

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> SFF ATA controllers are peculiar in that...
> 
> 1. it doesn't have reliable IRQ pending bit.
> 
> 2. it doesn't have reliable IRQ mask bit.
> 
> 3. some controllers tank the machine completely if status or data
> register is accessed differently than the chip likes.

And 4. which is a killer for a lot of RT users

An I/O cycle to a taskfile style controller generally goes at ISA type
speed down the wire to the drive and back again. The CPU is stalled for
this and there is nothing we can do about it.

> 
> So, it's not like we're all dickheads.  We know it's good to take those
> out of irq handler.  The hardware just isn't very forgiving and I bet
> you'll get obscure machine lockups if the RT kernel arbitrarily pushes
> ATA PIO data transfers into kernel threads.
> 
> I think doing what IDE has been doing (disabling IRQ from interrupt
> controller) is the way to go.

Agreed - at which point RT or otherwise you can push it out. If you need
to do serious (sub 1mS) ATA then also go get a non SFF controller.

Alan
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