Hi Bart, Thanks for the review feedback. On Fri, 28 Feb 2025 at 19:21, Bart Van Assche <bvanassche@xxxxxxx> wrote: > > On 2/26/25 2:04 PM, Peter Griffin wrote: > > GPIO_OUT[0] is connected to the reset pin of embedded UFS device. > > Before powering off the phy assert the reset signal. > Does the above apply to the GS implementation only or does it apply to > all SoC's with an Exynos UFS host controller? The reason I went with a generic approach (rather than adding another SoC specific hook) was that exynos_ufs_dev_hw_reset() is already called by all users of this driver. From that I concluded it is a common register shared by all exynos implementations. It is hard to be 100% sure though as I don't personally have any of the other Exynos platforms supported by this driver to test on. Another approach would be to add some more gs101 SoC specific hooks for suspend() and exit() to exynos_ufs_drv_data() or another EXYNOS_UFS_OPT_. Thanks, Peter
