On 13.01.2025 10:46 PM, Melody Olvera wrote:
> From: Nitin Rawat <quic_nitirawa@xxxxxxxxxxx>
>
> Add UFS host controller and PHY nodes for SM8750 SoC.
>
> Co-developed-by: Manish Pandey <quic_mapa@xxxxxxxxxxx>
> Signed-off-by: Manish Pandey <quic_mapa@xxxxxxxxxxx>
> Signed-off-by: Nitin Rawat <quic_nitirawa@xxxxxxxxxxx>
> Signed-off-by: Melody Olvera <quic_molvera@xxxxxxxxxxx>
> ---
I don't see anything wrong per se here, just some style nits
atop the other replies:
[...]
> + ufs_mem_hc: ufs@1d84000 {
> + compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1 compatible per lines, please
> + reg = <0x0 0x01d84000 0x0 0x3000>;
> +
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&rpmhcc RPMH_LN_BB_CLK3>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + clock-names = "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
> + freq-table-hz = <100000000 403000000>,
> + <0 0>,
> + <0 0>,
> + <100000000 403000000>,
> + <100000000 403000000>,
> + <0 0>,
> + <0 0>,
> + <0 0>;
> +
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> +
> +
stray double \n
Konrad
