On Wed, 2024-08-21 at 14:39 -0700, Bart Van Assche wrote: > On 8/21/24 2:27 PM, Bean Huo wrote: > > My only concern is, removing disabling UIC completion IRQ, and > > keeping > > is.uccs 1, then we don't read its status in case of > > ufshcd_uic_pwr_ctrl > > path, whether this will affect the next UIC access result. > > Hmm ... I think I need more context information. If the UIC > completion > interrupt is left enabled then ufshcd_intr() will execute the code > "intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS)". This > statement > reads all bits from the interrupt status register including the UCCS > bit, isn't it? > > Thanks, > > Bart. One UIC power ctrl command will generate two Compl interrupts, one is command complete (UIC_COMMAND_COMPL) and the other is power switch complete (UFSHCD_UIC_PWR_MASK). Is that right? I checked the current code and we don't read the UFSHCI registers except when we read intr status before ufshcd_uic_cmd_compl() and re-enable UIC compl interrupt. Do you mean re-enabling UIC complete interrupt will cause the problem? Kind regards, Bean
