Prepare so we'll be able to read various other HCI registers. While at it, fix the HCPID & HCMID register names to stand for what they really are. Signed-off-by: Avri Altman <avri.altman@xxxxxxx> --- drivers/ufs/core/ufs-sysfs.c | 38 +++++++++++++++++++++--------------- include/ufs/ufshci.h | 5 +++-- 2 files changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/ufs/core/ufs-sysfs.c b/drivers/ufs/core/ufs-sysfs.c index e80a32421a8c..7a264f8ef140 100644 --- a/drivers/ufs/core/ufs-sysfs.c +++ b/drivers/ufs/core/ufs-sysfs.c @@ -198,33 +198,39 @@ static u32 ufshcd_us_to_ahit(unsigned int timer) FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, scale); } -static ssize_t auto_hibern8_show(struct device *dev, - struct device_attribute *attr, char *buf) +static int ufshcd_read_hci_reg(struct ufs_hba *hba, u32 *val, unsigned int reg) { - u32 ahit; - int ret; - struct ufs_hba *hba = dev_get_drvdata(dev); - - if (!ufshcd_is_auto_hibern8_supported(hba)) - return -EOPNOTSUPP; - down(&hba->host_sem); if (!ufshcd_is_user_access_allowed(hba)) { - ret = -EBUSY; - goto out; + up(&hba->host_sem); + return -EBUSY; } pm_runtime_get_sync(hba->dev); ufshcd_hold(hba); - ahit = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); + *val = ufshcd_readl(hba, reg); ufshcd_release(hba); pm_runtime_put_sync(hba->dev); - ret = sysfs_emit(buf, "%d\n", ufshcd_ahit_to_us(ahit)); - -out: up(&hba->host_sem); - return ret; + return 0; +} + +static ssize_t auto_hibern8_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u32 ahit; + int ret; + struct ufs_hba *hba = dev_get_drvdata(dev); + + if (!ufshcd_is_auto_hibern8_supported(hba)) + return -EOPNOTSUPP; + + ret = ufshcd_read_hci_reg(hba, &ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); + if (ret) + return ret; + + return sysfs_emit(buf, "%d\n", ufshcd_ahit_to_us(ahit)); } static ssize_t auto_hibern8_store(struct device *dev, diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h index 38fe97971a65..194e3655902e 100644 --- a/include/ufs/ufshci.h +++ b/include/ufs/ufshci.h @@ -25,8 +25,9 @@ enum { REG_CONTROLLER_CAPABILITIES = 0x00, REG_MCQCAP = 0x04, REG_UFS_VERSION = 0x08, - REG_CONTROLLER_DEV_ID = 0x10, - REG_CONTROLLER_PROD_ID = 0x14, + REG_EXT_CONTROLLER_CAPABILITIES = 0x0C, + REG_CONTROLLER_PID = 0x10, + REG_CONTROLLER_MID = 0x14, REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, REG_INTERRUPT_STATUS = 0x20, REG_INTERRUPT_ENABLE = 0x24, -- 2.25.1