On 6/27/2024 10:05 PM, Bart Van Assche wrote:
On 6/27/24 1:37 AM, Ram Prakash Gupta wrote:
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 1b65e6ae4137..9f935e5c60e8 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -1560,7 +1560,8 @@ static int ufshcd_devfreq_target(struct device
*dev,
ktime_to_us(ktime_sub(ktime_get(), start)), ret);
out:
- if (sched_clk_scaling_suspend_work && !scale_up)
+ if (sched_clk_scaling_suspend_work &&
+ (!scale_up || hba->clk_scaling.suspend_on_no_request))
queue_work(hba->clk_scaling.workq,
&hba->clk_scaling.suspend_work);
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index bad88bd91995..c14607f2890b 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -457,6 +457,7 @@ struct ufs_clk_scaling {
bool is_initialized;
bool is_busy_started;
bool is_suspended;
+ bool suspend_on_no_request;
};
#define UFS_EVENT_HIST_LENGTH 8
Who are the other vendors that support clock scaling? I'm asking because
I don't think that the behavior change introduced by this patch should
depend on the SoC vendor.
Thanks,
Bart.
Hi Bart,
I guess, Mediatek is one vendor who is having this feature in use as I
see some fixes coming from Peter with respect to clk scaling, where some
power regression on mediatek chipsets were addressed.
Please check below link for background of this change and reason to keep
it vendor specific.
https://www.spinics.net/lists/linux-scsi/msg193591.html
Thanks,
Ram
