Hi André,
On Tue, 16 Apr 2024 at 13:21, André Draszik <andre.draszik@xxxxxxxxxx> wrote:
>
> Hi Pete,
>
> On Tue, 2024-04-16 at 12:56 +0100, Peter Griffin wrote:
> > Hi André,
> >
> > Thanks for the review.
> >
> > On Fri, 5 Apr 2024 at 08:38, André Draszik <andre.draszik@xxxxxxxxxx> wrote:
> > >
> > > On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> > > > Enable the cmu_hsi2 clock management unit. It feeds some of
> > > > the high speed interfaces such as PCIe and UFS.
> > > >
> > > > Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
> > > > ---
> > > > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> > > > 1 file changed, 12 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > > index eddb6b326fde..38ac4fb1397e 100644
> > > > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > > @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 {
> > > > interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
> > > > };
> > > >
> > > > + cmu_hsi2: clock-controller@14400000 {
> > > > + compatible = "google,gs101-cmu-hsi2";
> > > > + reg = <0x14400000 0x4000>;
> > > > + #clock-cells = <1>;
> > > > + clocks = <&ext_24_5m>,
> > > > + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
> > > > + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
> > > > + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
> > > > + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
> > > > + clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> > > > + };
> > >
> > > This doesn't build because you didn't add the clock ids in the binding patch.
> >
> > These clock IDs are for cmu_top, not cmu_hsi2.
>
> Right. I replied to the wrong patch. Sorry for that. It is patch 7 that
> uses clock ids that are only added in patch 8. The clock ids from patch 8
> in include/dt-bindings/clock/google,gs101.h should be added in patch 1
> instead.
Ah I see, thanks for the clarification. I'll fix that in v2.
Thanks,
Pete
