Chris, > -----Original Message----- > From: Chris Leech <cleech@xxxxxxxxxx> > Sent: Thursday, January 25, 2024 5:07 AM > To: Nilesh Javali <njavali@xxxxxxxxxxx> > Cc: martin.petersen@xxxxxxxxxx; lduncan@xxxxxxxx; linux- > scsi@xxxxxxxxxxxxxxx; GR-QLogic-Storage-Upstream <GR-QLogic-Storage- > Upstream@xxxxxxxxxxx>; jmeneghi@xxxxxxxxxx > Subject: [EXT] Re: [PATCH v3 1/3] uio: introduce UIO_MEM_DMA_COHERENT > type > > External Email > > ---------------------------------------------------------------------- > Nilesh, > > On Tue, Jan 09, 2024 at 05:44:56PM +0530, Nilesh Javali wrote: > > + ret = dma_mmap_coherent(&idev->dev, > > + vma, > > + addr, > > + mem->dma_addr, > > + vma->vm_end - vma->vm_start); > > When I asked about the use of idev->dev here in the v2 posting, you > repled as follows. > > > While the cnic loads, it registers the cnic_uio_dev->pdev->dev with > > uio and the uio attaches its device to cnic device as it's parent. So > > uio and cnic are attached to the same PCI device. > > I still don't think the sysfs parent relationship is enough to get the > correct behavior out of the DMA APIs on all platforms, and > dma_mmap_coherent needs to be using the same device struct as > dma_alloc_coherent. > > I had some testing done on an AMD system, where your v2 patch set was > failing with the iommu enabled, and my original changes were reported to > work. And I believe these v3 patches are functionally the same. We have extensively verified this patch set with IOMMU enabled and see no regression when VT and SRIOV are enabled. However issues are observed only when VT, VT-D and SRIOV are enabled in the HW BIOS. In the failure case, with VT-D enabled, we observe the OS fails to boot with DMAR timeout error. " **] A start job is running for Network Manager (2min 6s / no limit) [ 147.069016] DMAR: VT-d detected Invalidation Time-out Error: SID 0 [ 147.069016] DMAR: DRHD: handling fault status reg 40 [ 147.080924] DMAR: QI HEAD: Device-TLB Invalidation qw0 = 0xaf0300100003, qw1 = 0x7ffffffffffff001 [ 147.090207] DMAR: QI PRIOR: Invalidation Wait qw0 = 0x200000025, qw1 = 0x10005f634". With your proposed changes, please confirm if you see no issues with VT-D enabled on Intel/AMD platform. Also based on our observation the issue with VT-D enabled is not related to the current patch set under test. Thanks, Nilesh
