On Thu, Dec 21, 2023 at 01:09:55PM -0600, Andrew Halaney wrote: > Currently, the UIC_COMMAND_COMPL interrupt is disabled and a wmb() is > used to complete the register write before any following writes. > > wmb() ensures the writes complete in that order, but completion doesn't > mean that it isn't stored in a buffer somewhere. The recommendation for > ensuring this bit has taken effect on the device is to perform a read > back to force it to make it all the way to the device. This is > documented in device-io.rst and a talk by Will Deacon on this can > be seen over here: > > https://youtu.be/i6DayghhA8Q?si=MiyxB5cKJXSaoc01&t=1678 > > Let's do that to ensure the bit hits the device. Because the wmb()'s > purpose wasn't to add extra ordering (on top of the ordering guaranteed > by writel()/readl()), it can safely be removed. > > Fixes: d75f7fe495cf ("scsi: ufs: reduce the interrupts for power mode change requests") > Signed-off-by: Andrew Halaney <ahalaney@xxxxxxxxxx> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> - Mani > --- > drivers/ufs/core/ufshcd.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c > index bb603769b029..75a03ee9a1ba 100644 > --- a/drivers/ufs/core/ufshcd.c > +++ b/drivers/ufs/core/ufshcd.c > @@ -4240,7 +4240,7 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) > * Make sure UIC command completion interrupt is disabled before > * issuing UIC command. > */ > - wmb(); > + ufshcd_readl(hba, REG_INTERRUPT_ENABLE); > reenable_intr = true; > } > spin_unlock_irqrestore(hba->host->host_lock, flags); > > -- > 2.43.0 > -- மணிவண்ணன் சதாசிவம்
