On Thu, Dec 21, 2023 at 12:25:22PM -0600, Andrew Halaney wrote: > Currently, the CGC enable bit is written and then an mb() is used to > ensure that completes before continuing. > > mb() ensure that the write completes, but completion doesn't mean that > it isn't stored in a buffer somewhere. The recommendation for > ensuring this bit has taken effect on the device is to perform a read > back to force it to make it all the way to the device. This is > documented in device-io.rst and a talk by Will Deacon on this can > be seen over here: > > https://youtu.be/i6DayghhA8Q?si=MiyxB5cKJXSaoc01&t=1678 > > Let's do that to ensure the bit hits the device. Because the mb()'s > purpose wasn't to add extra ordering (on top of the ordering guaranteed > by writel()/readl()), it can safely be removed. > > Fixes: 81c0fc51b7a7 ("ufs-qcom: add support for Qualcomm Technologies Inc platforms") > Signed-off-by: Andrew Halaney <ahalaney@xxxxxxxxxx> For this patch, a read back would make sense since I'm not sure if the ICE block getting enabled afterwards is in the same domain or not. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> - Mani > --- > drivers/ufs/host/ufs-qcom.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c > index ab1ff7432d11..3db19591d008 100644 > --- a/drivers/ufs/host/ufs-qcom.c > +++ b/drivers/ufs/host/ufs-qcom.c > @@ -409,7 +409,7 @@ static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) > REG_UFS_CFG2); > > /* Ensure that HW clock gating is enabled before next operations */ > - mb(); > + ufshcd_readl(hba, REG_UFS_CFG2); > } > > static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, > > -- > 2.43.0 > -- மணிவண்ணன் சதாசிவம்
