On Fri, 2023-10-27 at 13:55 -0700, Bart Van Assche wrote: > > External email : Please do not click links or open attachments until > you have verified the sender or the content. > On 10/26/23 20:27, Chun-Hung Wu (巫駿宏) wrote: > > From UFSHCI 4.0 spec "When the head and tail doorbells are equal, > the > > queue is empty. *Nothe that this definition means there will always > be > > one empty queue entry" > > One of our platform does not keep one empty queue > > entry for CQ full > > case, that's why we need this patch to fix this corner case. > > The UFSHCI driver should make sure that there is always one empty > queue > entry. Does "platform" in the above text refer to the SoC that > includes > the UFSHCI controller? Yes here "platform" indicates SoC that includes the UFSHCI controller. > > What is totally unclear to me is why the following code depends on > the > UFSHCI controller type: > > +if (ufshcd_is_mcq_expand_queue_slot(hba)) > +hwq->max_entries = hba->nutrs + 1; > +else > +hwq->max_entries = hba->nutrs; > > Shouldn't hwq->max_entries = hba->nutrs + 1 be used for all UFSHCI > 4.0 > controllers? > > Thanks, > > Bart. > I think UFSHCI 4.0 spec "When the head and tail doorbells are equal,the queue is empty. *Nothe that this definition means there will alwaysbe one empty queue entry" means that "UFSHCI controller" should always keep one empty queue entry. One of our host does not follow the spec, therefore, this host will treat CQ full(head = tail) as CQ empty (head = tail). That's why we propose this quirk to expand one queue slot for hosts have such issue. It will make CQ full(head != tail)[keep one empty queue entry] not equal to CQ empty(head = tail). hwq->max_entries will be used to set SQ&CQ size in SQ&CQ Configuration Registers, we think it should only apply to specific hosts need this quirk not all. Thanks, Chun-Hung
