On Wed, Sep 27, 2023 at 04:45:46PM +0530, Viresh Kumar wrote: > On 12-09-23, 12:29, Manivannan Sadhasivam wrote: > > On Mon, Sep 11, 2023 at 04:15:10PM +0300, Dmitry Baryshkov wrote: > > > I'd say, I'm still slightly unhappy about the 0 clock rates here. > > > > Neither do I. But it is the only viable option I could found. > > > > > We need only three clocks here: core, core_clk_unipro and optional > > > ice_core_clk. Can we modify ufshcd_parse_operating_points() to pass only > > > these two or three clock names to devm_pm_opp_set_config() ? The OPP core > > > doesn't need to know about all the rest of the clocks. > > > > > > > We need to enable/disable all of the clocks, but only need to control the rate > > for these 3 clocks. So we cannot just use 3 clocks. > > > > If the OPP table has only 3 entries (omitting the gate-only clocks), then we > > need some hack in the driver to match the rates against the clock entries. Doing > > so will result in hardcoding the clock info in the driver which I do not want to > > do. > > > > If we have something like "opp-hz-names" to relate the rates to clock-names, it > > might do the job. But it needs some input from Viresh. > > I have already given an option earlier about this [1]. You can change the order > of clks in the "clock-names" field, so that the first three are the one with > valid frequencies. You shouldn't need much of the hacks after that I guess. > I do not remember all the details on the top of my head, but I did investigate on that and concluded that it won't fit. - Mani > Or maybe I missed something else now, talked about this a long time ago :) > > -- > viresh > [1] https://lore.kernel.org/all/20230713040918.jnf5oqiwymrdnrmq@vireshk-i7/ -- மணிவண்ணன் சதாசிவம்
