On Sun, Oct 30, 2022 at 12:48:21AM +0300, Dmitry Baryshkov wrote:
> On 29/10/2022 17:16, Manivannan Sadhasivam wrote:
> > Starting from UFS controller v4, Qcom supports dual gear mode (i.e., the
> > controller/PHY can be configured to run in two gear speeds). But that
> > requires an agreement between the UFS controller and the UFS device.
> > This commit finds the max gear supported by both controller and device
> > then decides which one to use.
> >
> > UFS controller's max gear can be read from the REG_UFS_PARAM0 register and
> > UFS device's max gear can be read from the "max-gear" devicetree property.
> >
> > The UFS PHY also needs to be configured with the decided gear using the
> > phy_set_mode_ext() API.
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> > ---
> > drivers/ufs/host/ufs-qcom.c | 35 ++++++++++++++++++++++++++++++++---
> > drivers/ufs/host/ufs-qcom.h | 4 ++++
> > 2 files changed, 36 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> > index f952cc76919f..268463e92d67 100644
> > --- a/drivers/ufs/host/ufs-qcom.c
> > +++ b/drivers/ufs/host/ufs-qcom.c
> > @@ -281,6 +281,9 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba)
> > static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba, u32 hs_gear)
> > {
> > struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> > + struct device *dev = hba->dev;
> > + u32 max_gear, hcd_max_gear, reg;
> > + int ret;
> > if (host->hw_ver.major == 0x1) {
> > /*
> > @@ -292,8 +295,33 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba, u32 hs_gear)
> > */
> > if (hs_gear > UFS_HS_G2)
> > return UFS_HS_G2;
> > + } else if (host->hw_ver.major > 0x3) {
> > + /*
> > + * Starting from UFS controller v4, Qcom supports dual gear mode (i.e., the
> > + * controller/PHY can be configured to run in two gear speeds). But that
> > + * requires an agreement between the UFS controller and the device. Below
> > + * code tries to find the max gear of both and decides which gear to use.
> > + *
> > + * First get the max gear supported by the UFS device if available.
> > + * If the property is not defined in devicetree, then use the default gear.
> > + */
> > + ret = of_property_read_u32(dev->of_node, "max-gear", &max_gear);
> > + if (ret)
> > + goto err_out;
>
> Can we detect the UFS device's max gear somehow? If not, the 'max-gear'
> property name doesn't sound good. Maybe calling it 'device-gear' would be
> better.
>
> > +
> > + /* Next get the max gear supported by the UFS controller */
> > + reg = ufshcd_readl(hba, REG_UFS_PARAM0);
> > + hcd_max_gear = UFS_QCOM_MAX_GEAR(reg);
> > +
> > + /*
> > + * Now compare both the gears. If the max gear supported by the UFS device
> > + * is compatible with UFS controller, then use the UFS device's max gear
> > + * speed. Otherwise, use the UFS controller supported max gear speed.
> > + */
> > + return (max_gear <= hcd_max_gear) ? max_gear : hcd_max_gear;
>
> return max(max_gear, hcd_max_gear); ?
>
min() should work...
Thanks,
Mani
> > }
> > +err_out:
> > /* Default is HS-G3 */
> > return UFS_HS_G3;
> > }
> > @@ -303,7 +331,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> > struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> > struct phy *phy = host->generic_phy;
> > int ret;
> > - bool is_rate_B = UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B;
> > + u32 hs_gear;
> > /* Reset UFS Host Controller and PHY */
> > ret = ufs_qcom_host_reset(hba);
> > @@ -311,8 +339,9 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> > dev_warn(hba->dev, "%s: host reset returned %d\n",
> > __func__, ret);
> > - if (is_rate_B)
> > - phy_set_mode(phy, PHY_MODE_UFS_HS_B);
> > + /* UFS_HS_G2 is used here since that's the least gear supported by legacy Qcom platforms */
> > + hs_gear = ufs_qcom_get_hs_gear(hba, UFS_HS_G2);
> > + phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, hs_gear);
> > /* phy initialization - calibrate the phy */
> > ret = phy_init(phy);
> > diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
> > index 214ea50acab9..c93bc52ea848 100644
> > --- a/drivers/ufs/host/ufs-qcom.h
> > +++ b/drivers/ufs/host/ufs-qcom.h
> > @@ -89,6 +89,10 @@ enum {
> > #define TMRLUT_HW_CGC_EN BIT(6)
> > #define OCSC_HW_CGC_EN BIT(7)
> > +/* bit definitions for REG_UFS_PARAM0 */
> > +#define MAX_HS_GEAR_MASK GENMASK(6, 4)
> > +#define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x))
> > +
> > /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
> > #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */
>
> --
> With best wishes
> Dmitry
>
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