On Mon, Sep 26 2022 at 08:46 -0700, Manivannan Sadhasivam wrote:
On Thu, Sep 22, 2022 at 06:05:14PM -0700, Asutosh Das wrote:
To read the bqueuedepth, the device descriptor is fetched
in Single Doorbell Mode. This allocated memory may not be
enough for MCQ mode because the number of tags supported
in MCQ mode may be larger than in SDB mode.
Hence, release the memory allocated in SDB mode and allocate
memory for MCQ mode operation.
Defines the ufs hardware queue and Completion Queue Entry.
Co-developed-by: Can Guo <quic_cang@xxxxxxxxxxx>
Signed-off-by: Can Guo <quic_cang@xxxxxxxxxxx>
Signed-off-by: Asutosh Das <quic_asutoshd@xxxxxxxxxxx>
---
drivers/ufs/core/ufs-mcq.c | 59 ++++++++++++++++++++++++++++++++++++++++--
drivers/ufs/core/ufshcd-priv.h | 1 +
drivers/ufs/core/ufshcd.c | 39 +++++++++++++++++++++++++---
include/ufs/ufshcd.h | 19 ++++++++++++++
include/ufs/ufshci.h | 21 +++++++++++++++
5 files changed, 134 insertions(+), 5 deletions(-)
[...]
diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h
index 6d16beb..f624682 100644
--- a/drivers/ufs/core/ufshcd-priv.h
+++ b/drivers/ufs/core/ufshcd-priv.h
@@ -52,6 +52,7 @@ int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
int ufshcd_mcq_init(struct ufs_hba *hba);
u32 ufshcd_mcq_decide_queue_depth(struct ufs_hba *hba);
+int ufshcd_mcq_memory_alloc(struct ufs_hba *hba);
#define SD_ASCII_STD true
#define SD_RAW false
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index a71b57e..5fc1e5e 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -3676,6 +3676,8 @@ static int ufshcd_memory_alloc(struct ufs_hba *hba)
goto out;
}
+ if (hba->utmrdl_base_addr)
+ goto skip_utmrdl;
Is this change belongs to this patch?
Yes.
This change frees and reallocates the descriptor memory by calling
ufshcd_memory_alloc() if MCQ is supported and configured, see
ufshcd_config_mcq().
I will add a comment here.
-asd
--
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