From: Peter Wang <peter.wang@xxxxxxxxxxxx> Some UFSHCI hosts in MediaTek UFS platform need workaround to prevent host hang issue by setting CLK_CG bit before host is enabled. This operation shall have no side effect on those platforms which do not support this bit. Reviewed-by: Stanley Chu <stanley.chu@xxxxxxxxxxxx> Signed-off-by: Peter Wang <peter.wang@xxxxxxxxxxxx> Signed-off-by: Stanley Chu <stanley.chu@xxxxxxxxxxxx> --- drivers/ufs/host/ufs-mediatek.c | 8 ++++++++ drivers/ufs/host/ufs-mediatek.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index f76e2999ac99..d6b2734e7f81 100755 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -183,6 +183,14 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT; hba->ahit = 0; } + + /* + * Turn on CLK_CG early to bypass abnormal ERR_CHK signal + * to prevent host hang issue + */ + ufshcd_writel(hba, + ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80, + REG_UFS_XOUFS_CTRL); } return 0; diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h index 49a2137fb251..f5c1c643dd52 100755 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -12,6 +12,7 @@ /* * Vendor specific UFSHCI Registers */ +#define REG_UFS_XOUFS_CTRL 0x140 #define REG_UFS_REFCLK_CTRL 0x144 #define REG_UFS_EXTREG 0x2100 #define REG_UFS_MPHYCTRL 0x2200 -- 2.18.0
